The invention relates to a method and mechanism for designing, placing, and routing an integrated circuit (“IC”).
An IC is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are “placed and routed” on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
For many designers, a goal of the IC design process is to place as many components as possible within the smallest possible area on an IC chip. A number of advantages exist by being able to place greater densities of components on the chip. For example, squeezing more components onto a chip allows smaller chips to be made, increasing the number of chips from a given production run as compared to larger chip sizes. In addition, increasing the density of components on an IC allows a greater number of the components to be placed on the chip, which facilitates an increase in chip functionality.
Consider the process to place and route a chip. A typical problem faced by the designer (or the designer's electronic design automation (“EDA”) tool) is how to place shapes on the chip or route wires through the chip when there are already existing objects and wires on the chip floorplan. In many cases, the designer is able to identify the most efficient path/location to route a wire or to place a shape, but is unable to place/route in that location because that exact position on the chip is already occupied by other shapes or wires. Even if the exact location on the chip is unoccupied, design/manufacturing rules may not allow the designer to locate an object in that location. Moreover, even if sufficient space is available and can legally allow placement/routing of an object, many EDA tools cannot efficiently identify the optimal way to place/route objects in the space close to other objects to maximize density of components. The solution in many cases is to move the shape to an alternate and possibly less preferred location or to route the wire through another path, which may be an inefficient and more convoluted path.